Our Services cover various industry segments that include:
With the hardware market booming with the rise demand in chip driven products in consumer electronics, medical electronics, communication, aero-space, computers etc. More and more chip designing companies have set up their units in India eying on the Indian talents; besides many of the Indian Major IT companies have forayed in ASIC design in a big way.
With the design & manufacturing market (both domestic & international) expanding rapidly, there is an enhanced demand of trained professionals who will boost the technical work force in this domain.
Our course on VLSI revolves mainly on ASIC, and the course layout is under final stage of completion. The admissions for the same will be done through an All India Entrance Test.
| Digital Design Fundamentals: |
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- Digital Design Fundamentals
- Advanced Digital Design
- Introduction to IC Design/Different Methodologies for IC Design
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| CMOS Theory and Implementation: |
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- MOS Fundamentals and Characterization
- NMOS/ PMOS/ CMOS Technologies
- Fabrication Principles
- Different Styles of Fabrication for NMOS/PMOS/CMOS
- Design with CMOS Gates
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- Characterization of CMOS Circuits
- Scaling Effects
- Sub-Micron Designs
- Parasitic Extraction and Calculations
- Subsystem Design
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- Stick Diagram/ Color Coding Modeling
- Design Exercise using CMOS
- CIF Format and Generation
- Design Exercise using CMOS
- Fabrication Flows and Fundamentals
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| Verlog/VHDL |
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- Modeling with HDL's
- Design Flows for IC Design
- VHDL/Verilog Basics
- Data Types and Process/Package Design
- Sequential and Concurrent Designs
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- State Machine Design
- Representation of Digital Circuit using VHDL/Verilog
- Simulation of Digital Designs
- Types of Test Benchs
- Writing Test Bench
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- Adding BIST in the Design using VHDL/Verilog
- Advanced VHDL Concepts
- VHDL/Verilog for Synthesis
- RTL Coding Styles and Guidelines
- ASIC Flow
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| Advanced Verlog/VHDL |
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- EDA-Tools/ CAD Flow for IC Design
- Simulation (Behavioral and Timing)
- Gate level Synthesis
- Static Timing Analysis
- Design for Testability (DFT) fundamentals
- Scan Diagnostics
- Logic BIST, Memory BIST
- ATPG, Boundary Scan
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- Compression
- Placing and Routing
- Re-configurable Designs, FPGA's, CPLD's
- Xilinx FPGA Archhitectures & FPGA families
- Altera FPGA Architectures & FPGA families
- Xilinx and Altera CPLD architecture
- FPGA and CPLD Design flow
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- Design using FPGA and CPLD
- Simulation and synthesys using FPGA libraries
- Implementation using FPGA and report analysis
- System On Chip Fundamentals
- Future trends and Challenges
- Project work/Hands on experience with Industry standard tools
- Prototyping using state of the art FPGA boa
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